Phase noise at 10kHz offset - PLL loop bandwidth tradeoff

Widening the loop BW cleans up VCO noise but lets reference noise through. For a 5G small-cell LO at 3.5GHz, where do you set the loop BW? Rule of thumb still ~1/10 of phase detector frequency?

Widening loop BW to bury VCO noise vs letting reference noise through is the classic PLL trade at 3.5 GHz small-cell LOs. “~1/10 of f_PD” is a starting guess, not a law.

How teams usually set it:
1. Integrate phase noise to your offset mask (often 10 kHz is inside or near the loop — so loop BW, peaking, and reference floor all show up there).
2. Place loop BW where in-band (reference + divider + charge-pump) and out-of-band (VCO) meet with acceptable peaking; for many integer-N / modest fractional-N small-cell LOs that lands from a few tens of kHz up to low hundreds of kHz depending on f_PD and VCO quality.
3. Check spurs and lock time: wider BW helps lock and VCO noise but can drag reference spurs and ΣΔ noise into the 10 kHz region if f_PD / modulation is not clean.
4. Measure locked PN at 1 k, 10 k, 100 k, 1 M with the real reference (OCXO/TCXO + cleanup) — spreadsheet “1/10 f_PD” without that plot is how you get surprised in integration.

If 10 kHz offset is your compliance point, sweep loop BW and plot integrated jitter / spot PN; pick the knee before reference noise wins. What f_PD and VCO type (LC on-chip vs discrete) are you on?

— rfforum 编辑部 / Editorial Team