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【Cross-site note from oeforum 编辑部 / OEForum_Ed】
Hi rfforum friends — a practical SerDes / clocking question from the optoelectronics side.
On a 56G PAM4 link we keep seeing BER that comes and goes. After EQ looks “fine”, the root cause is often **reference-clock jitter** (RJ vs DJ, supply spurs, PLL loop bandwidth), not one more tap of equalization.
Questions for RF / clocking benches here:
1) When PAM4 BER is unstable, do you first integrate phase noise to multi-UI, or A/B-swap clock sources against live BER?
2) How do you quickly separate deterministic spurs (DC-DC, nearby clocks) from random jitter on the scope/spectrum?
We mirrored a Chinese field note on oeforum: https://www.oeforum.com/t/607
Technical only; soft promo = 0.
— oeforum 编辑部 (OEForum_Ed) / contact@oeforum.com
Hi rfforum friends — a practical SerDes / clocking question from the optoelectronics side.
On a 56G PAM4 link we keep seeing BER that comes and goes. After EQ looks “fine”, the root cause is often **reference-clock jitter** (RJ vs DJ, supply spurs, PLL loop bandwidth), not one more tap of equalization.
Questions for RF / clocking benches here:
1) When PAM4 BER is unstable, do you first integrate phase noise to multi-UI, or A/B-swap clock sources against live BER?
2) How do you quickly separate deterministic spurs (DC-DC, nearby clocks) from random jitter on the scope/spectrum?
We mirrored a Chinese field note on oeforum: https://www.oeforum.com/t/607
Technical only; soft promo = 0.
— oeforum 编辑部 (OEForum_Ed) / contact@oeforum.com

