R
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Most impedance matching starts as a two-element L-match exercise, then real boards force you into Pi/T layouts and the design intuitions from the textbook quietly break. This post is a field guide to Q — the parameter tying those topologies together.
1. The one rule for L-networks
For a given R_source → R_load transformation at a fixed frequency, the L-network is not unique: two solutions exist (series-L/shunt-C and series-C/shunt-L), each with a loaded-Q set by the ratio alone:
Q = sqrt(R_high/R_low − 1)
Consequence that surprises people: bandwidth is fixed by the impedance ratio, not by your creativity. Need narrower band than the L gives you? Add reactive elements — but that's where Pi/T enters.
2. What Pi actually buys you
A Pi network is two L-sections cascaded through a virtual middle resistance R_m you choose. The choice of R_m sets:
- R_m = sqrt(R₁·R₂) → equal-Q symmetric case, good baseline;
- R_m > sqrt(R₁·R₂) → higher Q → narrower bandwidth, lower harmonic (PA output!), but more circulating current → more loss in real inductors.
The practical failure mode: engineers pick high Q "for harmonic filtering", then measure insertion loss, and find dBs gone in the inductor. Rule of thumb: circulating current in the C element of a Q=8 section can be several amps at 50 W PA power levels with tens of mΩ ESR parts. Count real component loss before trusting sim (use the vendor S2P models of the 0201/0402 parts, not ideal L/C).
3. Source/load Q classification (the useful mental model)
- R_source ≫ R_load in some sense, low-Q devices like GaN FETs: match output capacitance C_ds as part of the network (series L first).
- High-Q resonant loads (SAW filters, antennas near resonance): matching network Q must stay well below load Q or the match becomes hypersensitive to process/temperature.
4. Layout: the element nobody simulations
On laminate at 2–6 GHz the dominant unmodeled effects in these sections are:
1. Shorted-stub from grounding vias — a 0.6 mm through via under a shunt cap is ~1 nH that shifts a 500 nH inductor by 10%+; model it or use bottom-grounded pads / via arrays per vendor guidance;
2. Pad/trace parasitics at component terminals (typ. 0.05–0.15 pF each side on 0402 — small, but decisive at 6 GHz);
3. Return-path discontinuities when crossing split planes between L and C — the "matching" is in fact transforming the ground.
5. Decision list next time
- Just need conjugate match at one tone → L (pick topology for DC-block and bias convenience first).
- Need band control or 2nd-harmonic compliance → Pi with R_m set from required BW, then loss-check every real part.
- Tuning budget zero and cheap harmonics matter → hybrid: L for transformation + single-section harmonic lowpass, simulate both under 20 % Monte-Carlo on the capacitors (class-2 ceramics laugh at ±10 %; use C0G in matching).
What loss do you measure on 0402 matching inductor at your band, real boards? I've seen 3 dB "budgeted" in a production LNA input match that survived AQL — curious about the community's floor values.
1. The one rule for L-networks
For a given R_source → R_load transformation at a fixed frequency, the L-network is not unique: two solutions exist (series-L/shunt-C and series-C/shunt-L), each with a loaded-Q set by the ratio alone:
Q = sqrt(R_high/R_low − 1)
Consequence that surprises people: bandwidth is fixed by the impedance ratio, not by your creativity. Need narrower band than the L gives you? Add reactive elements — but that's where Pi/T enters.
2. What Pi actually buys you
A Pi network is two L-sections cascaded through a virtual middle resistance R_m you choose. The choice of R_m sets:
- R_m = sqrt(R₁·R₂) → equal-Q symmetric case, good baseline;
- R_m > sqrt(R₁·R₂) → higher Q → narrower bandwidth, lower harmonic (PA output!), but more circulating current → more loss in real inductors.
The practical failure mode: engineers pick high Q "for harmonic filtering", then measure insertion loss, and find dBs gone in the inductor. Rule of thumb: circulating current in the C element of a Q=8 section can be several amps at 50 W PA power levels with tens of mΩ ESR parts. Count real component loss before trusting sim (use the vendor S2P models of the 0201/0402 parts, not ideal L/C).
3. Source/load Q classification (the useful mental model)
- R_source ≫ R_load in some sense, low-Q devices like GaN FETs: match output capacitance C_ds as part of the network (series L first).
- High-Q resonant loads (SAW filters, antennas near resonance): matching network Q must stay well below load Q or the match becomes hypersensitive to process/temperature.
4. Layout: the element nobody simulations
On laminate at 2–6 GHz the dominant unmodeled effects in these sections are:
1. Shorted-stub from grounding vias — a 0.6 mm through via under a shunt cap is ~1 nH that shifts a 500 nH inductor by 10%+; model it or use bottom-grounded pads / via arrays per vendor guidance;
2. Pad/trace parasitics at component terminals (typ. 0.05–0.15 pF each side on 0402 — small, but decisive at 6 GHz);
3. Return-path discontinuities when crossing split planes between L and C — the "matching" is in fact transforming the ground.
5. Decision list next time
- Just need conjugate match at one tone → L (pick topology for DC-block and bias convenience first).
- Need band control or 2nd-harmonic compliance → Pi with R_m set from required BW, then loss-check every real part.
- Tuning budget zero and cheap harmonics matter → hybrid: L for transformation + single-section harmonic lowpass, simulate both under 20 % Monte-Carlo on the capacitors (class-2 ceramics laugh at ±10 %; use C0G in matching).
What loss do you measure on 0402 matching inductor at your band, real boards? I've seen 3 dB "budgeted" in a production LNA input match that survived AQL — curious about the community's floor values.
