L
Admin
A lot of early-career RF spins fail the same way: the schematic is "matched," the layout looks clean, and the first bring-up burns a week because nobody decided **which five measurements are the gate** before ordering more boards.
This is the gate list I wish I had on spin #1 (sub-6 GHz radio / front-end style boards). Not a career essay — a bring-up contract.
**1. DC / bias map before any RF**
Rail voltages, current per rail, sequencer order, and "enable then RF" vs "RF then enable." Half of "dead LNA" tickets are bias or sequencing.
**2. Unpowered continuity / shorts on RF nets**
DC ohmmeter across RF paths that should be blocked by series C; shorts to ground on bias tees; wrong footprint bridges. Cheap, saves a fried first sample.
**3. S11 / S22 at the connector with a known cal**
Not "looks matched in sim" — measured at the launch you will ship. Log cal kit, torque, and cable ID next to the screenshot (Chinese Corner thread on daily lab checklist applies here too).
**4. One absolute level path**
CW in → CW out (or noise figure / gain) at a single frequency with pads and SA/VNA settings written down. Relative "it makes a tone" is not a gate.
**5. Spur / supply sanity under modulation or keyed TX**
Even a crude ACLR / harmonic check at one channel catches PA instability, missing decoupling, and LO leakage before you optimize EVM.
**What I deliberately leave out of spin-1 gates**
Full OTA pattern, full temp suite, and every corner case — those are spin-2. Spin-1 is "does the chain behave like the block diagram on the bench."
**Discussion**
On your first (or last) RF spin, which single measurement would you add to this five — and which one do juniors most often skip?
— rfforum 编辑部 / Editorial Team
This is the gate list I wish I had on spin #1 (sub-6 GHz radio / front-end style boards). Not a career essay — a bring-up contract.
**1. DC / bias map before any RF**
Rail voltages, current per rail, sequencer order, and "enable then RF" vs "RF then enable." Half of "dead LNA" tickets are bias or sequencing.
**2. Unpowered continuity / shorts on RF nets**
DC ohmmeter across RF paths that should be blocked by series C; shorts to ground on bias tees; wrong footprint bridges. Cheap, saves a fried first sample.
**3. S11 / S22 at the connector with a known cal**
Not "looks matched in sim" — measured at the launch you will ship. Log cal kit, torque, and cable ID next to the screenshot (Chinese Corner thread on daily lab checklist applies here too).
**4. One absolute level path**
CW in → CW out (or noise figure / gain) at a single frequency with pads and SA/VNA settings written down. Relative "it makes a tone" is not a gate.
**5. Spur / supply sanity under modulation or keyed TX**
Even a crude ACLR / harmonic check at one channel catches PA instability, missing decoupling, and LO leakage before you optimize EVM.
**What I deliberately leave out of spin-1 gates**
Full OTA pattern, full temp suite, and every corner case — those are spin-2. Spin-1 is "does the chain behave like the block diagram on the bench."
**Discussion**
On your first (or last) RF spin, which single measurement would you add to this five — and which one do juniors most often skip?
— rfforum 编辑部 / Editorial Team
