L
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Port setup threads usually debate wave vs lumped. The quieter failure mode is **reference-plane discipline once you already chose a wave port**.
At 20 GHz, 0.1 mm of unaccounted line is not academic:
- In air, 0.1 mm ≈ 2.4° of phase at 20 GHz (order-of-magnitude; dielectric slows it further).
- Cascaded filter / duplexer / via-transition models that each "look fine" can disagree with the assembled S-params by several degrees and a few tenths of dB of ripple — enough to chase the wrong resonator.
**Habits that keep teams honest**
1. **Name the reference plane in the report** (connector reference, via barrel top, pad edge) — not "at the port."
2. Prefer **de-embed / shift to a documented plane** that matches the fixture you will measure (same 2x-thru or unknown-thru story as in the TDR vs VNA thread).
3. When comparing sim ↔ VNA, compare **Δ between two states** at the same plane (loaded vs unloaded, filter A vs thru) before arguing absolute S11.
4. Do not "fix" a phase error by nudging port length until the plot is pretty unless you also update the mechanical drawing and the fixture model.
**Minimum port block in a design review**
- Port type (wave/lumped) and why
- Reference plane location + any auto-length correction
- Mode / impedance check at band edges
- How the same plane will be realized on the VNA fixture
**Discussion**
What reference-plane convention does your team enforce on multi-block cascades — and where have you seen a 0.1 mm-class shift waste the most debug time?
— rfforum 编辑部 / Editorial Team
At 20 GHz, 0.1 mm of unaccounted line is not academic:
- In air, 0.1 mm ≈ 2.4° of phase at 20 GHz (order-of-magnitude; dielectric slows it further).
- Cascaded filter / duplexer / via-transition models that each "look fine" can disagree with the assembled S-params by several degrees and a few tenths of dB of ripple — enough to chase the wrong resonator.
**Habits that keep teams honest**
1. **Name the reference plane in the report** (connector reference, via barrel top, pad edge) — not "at the port."
2. Prefer **de-embed / shift to a documented plane** that matches the fixture you will measure (same 2x-thru or unknown-thru story as in the TDR vs VNA thread).
3. When comparing sim ↔ VNA, compare **Δ between two states** at the same plane (loaded vs unloaded, filter A vs thru) before arguing absolute S11.
4. Do not "fix" a phase error by nudging port length until the plot is pretty unless you also update the mechanical drawing and the fixture model.
**Minimum port block in a design review**
- Port type (wave/lumped) and why
- Reference plane location + any auto-length correction
- Mode / impedance check at band edges
- How the same plane will be realized on the VNA fixture
**Discussion**
What reference-plane convention does your team enforce on multi-block cascades — and where have you seen a 0.1 mm-class shift waste the most debug time?
— rfforum 编辑部 / Editorial Team
