P
Member
100W wireless charger at 6.78MHz, harmonics are everywhere. Shielding helps but the coil itself radiates. How are people passing radiated emissions on high-power WPT?
EMI from 100W wireless charging - passing FCC Part 18?
L
Admin
On 6.78 MHz / ~100 W WPT, the coil is the coupler — you will not “shield it away” and still keep efficiency. What actually passes Part 18 (and the Part 15 digital / cable baggage that rides along) is usually **harmonic / CM control**, not a thicker can around the pad.
1. **Split the problem (what fails first on our travellers)**
- **Fundamental H-field** at 6.78 MHz: intentional; budget against the Part 18 ISM field-strength / distance table you are gating, with the manufacturer’s coil geometry and the worst allowed misalignment / foreign-object case. A Faraday lid over the coil kills coupling — do not start there.
- **Harmonics of the inverter** (2f0, 3f0, … into HF/VHF): almost always the RE fail when “shielding helped a bit.” Class-D/E edges + coil lead loop area = a small MF/HF transmitter.
- **Common-mode on DC in, USB-PD, chassis, and long sense leads**: shows up as RE that moves when you clamp a ferrite on the cable — classic “coil radiates” misdiagnosis.
2. **What we change before another shield spin**
- **Inverter edges:** soft-switching / resonant Class-E (or well-snubbed Class-D), gate-drive shaping, and a **series harmonic trap** (or at least a tight LP) between bridge and coil. Target 2f0/3f0 current in the coil feed, not only faceplate E-field.
- **Loop area:** power-stage + coil-feed loop kept tiny and tight to the return; twist or sandwich the coil leads; do not let the 100 W AC current enclose a credit-card-sized area on the PCB.
- **Balance / CM:** differential or tightly coupled coil drive; CM choke on the coil pair if the topology allows; clamp-on ferrites on every cable that leaves the product for the first RE triage.
- **One-sided magnetics, not a sealed can:** ferrite backing / field shaper behind the Tx coil to cut backside / edge radiation without enclosing the coupling face. That is the shield that still ships.
- **Digital / SMPS:** treat the MCU/PD controller as a Part 15 companion — separate return discipline and cable CM, or the WPT pad gets blamed for clock harmonics.
3. **How we gate “ready for the lab”**
- Near-field H-loop survey at 2f0/3f0 around coil, inverter, and cable exits **before** chamber time — chamber should confirm, not discover.
- Same sweep with coil unloaded / loaded / misaligned; harmonic RE often peaks off the efficiency sweet spot.
- Log inverter topology, gate rise time, trap presence, and which cable ferrite moved the peak — without that, “shielding helped” is not reproducible.
Open: are you failing on **harmonics (HF/VHF)** or on the **6.78 MHz fundamental** field table — and is the inverter Class-E resonant or hard-switched? That split usually decides trap/layout vs “we need a different coil/field-shaper,” before another enclosure revision.
— rfforum 编辑部 / Editorial Team
1. **Split the problem (what fails first on our travellers)**
- **Fundamental H-field** at 6.78 MHz: intentional; budget against the Part 18 ISM field-strength / distance table you are gating, with the manufacturer’s coil geometry and the worst allowed misalignment / foreign-object case. A Faraday lid over the coil kills coupling — do not start there.
- **Harmonics of the inverter** (2f0, 3f0, … into HF/VHF): almost always the RE fail when “shielding helped a bit.” Class-D/E edges + coil lead loop area = a small MF/HF transmitter.
- **Common-mode on DC in, USB-PD, chassis, and long sense leads**: shows up as RE that moves when you clamp a ferrite on the cable — classic “coil radiates” misdiagnosis.
2. **What we change before another shield spin**
- **Inverter edges:** soft-switching / resonant Class-E (or well-snubbed Class-D), gate-drive shaping, and a **series harmonic trap** (or at least a tight LP) between bridge and coil. Target 2f0/3f0 current in the coil feed, not only faceplate E-field.
- **Loop area:** power-stage + coil-feed loop kept tiny and tight to the return; twist or sandwich the coil leads; do not let the 100 W AC current enclose a credit-card-sized area on the PCB.
- **Balance / CM:** differential or tightly coupled coil drive; CM choke on the coil pair if the topology allows; clamp-on ferrites on every cable that leaves the product for the first RE triage.
- **One-sided magnetics, not a sealed can:** ferrite backing / field shaper behind the Tx coil to cut backside / edge radiation without enclosing the coupling face. That is the shield that still ships.
- **Digital / SMPS:** treat the MCU/PD controller as a Part 15 companion — separate return discipline and cable CM, or the WPT pad gets blamed for clock harmonics.
3. **How we gate “ready for the lab”**
- Near-field H-loop survey at 2f0/3f0 around coil, inverter, and cable exits **before** chamber time — chamber should confirm, not discover.
- Same sweep with coil unloaded / loaded / misaligned; harmonic RE often peaks off the efficiency sweet spot.
- Log inverter topology, gate rise time, trap presence, and which cable ferrite moved the peak — without that, “shielding helped” is not reproducible.
Open: are you failing on **harmonics (HF/VHF)** or on the **6.78 MHz fundamental** field table — and is the inverter Class-E resonant or hard-switched? That split usually decides trap/layout vs “we need a different coil/field-shaper,” before another enclosure revision.
— rfforum 编辑部 / Editorial Team
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