N
Member
Want to do direct sampling at 28GHz, need 60GS/s ADCs that cost more than my house. Is sub-sampling with a good track-and-hold still the practical route for mmWave SDR prototypes?
SDR for mmWave - ADC sampling rate wall
L
Admin
Short answer for prototypes: **yes — sub-sampling with a heroic T/H is still *possible*, but a mmWave → IF (or zero-IF I/Q) front-end + sane-rate ADCs is still what we ship and what most benches keep working.** Direct 60 GS/s at 28 GHz is a purchasing problem *and* a clock/jitter problem.
1. **Why “just undersample 28 GHz” bites**
- Bandpass sampling needs the ADC/T/H **analog input bandwidth ≥ carrier**, not only fs > 2·B. A 5 GS/s converter with 1.5 GHz input BW does not see 28 GHz no matter which Nyquist zone you write on the whiteboard.
- Aperture jitter: SNR_jitter ≈ −20·log10(2π·f_in·t_j). At **f_in = 28 GHz**, even a loose **40 dB** SNR budget wants t_j on the order of **~18 fs RMS** (RSS of clock + ADC aperture). That is research-grade clocking + T/H, not an eval-board balun and a “low-jitter” CMOS PLL.
- So the wall is often **jitter × input BW**, not the sticker GS/s. A 60 GS/s part with mediocre aperture jitter still folds 28 GHz into mush.
2. **Practical prototype routes (what we actually bring up)**
1) **mmWave I/Q or single-mixer → IF, then RF-sampling / HS ADC** — still the default. Buy or module a 26–30 GHz downconverter (or beamformer IC with IF out), put anti-alias where it is cheap, sample at GS/s class. You own image / LO leakage / I/Q balance, which is easier than 20 fs at 28 GHz.
2) **Integrated mmWave RFSoC / FEMs** — when the SKU exists for your band: treat the on-chip mixer+ADC as the sampler; do not recreate it with a discrete 60 GS/s.
3) **True RF sampling at 28 GHz with external T/H** — reserved for demos where the T/H aperture and clock are the programme. Budget the jitter stack on paper before you PO the ADC; if you cannot name t_j and the clock tree, you are buying a very expensive IF aliaser.
3. **When sub-sampling *does* earn its keep**
- Carriers where commercial ADCs already have the **input BW** (roughly sub-6 to low-teens GHz today, part-dependent) and you can hold **≤50–100 fs** class jitter for your SNR target.
- Narrow instantaneous BW with heavy averaging / processing gain — still does not relax the *jitter* SNR floor on a CW tone; it only helps after the sampler is already clean enough.
- For a **28 GHz SDR prototype** whose goal is waveforms / beam / protocol, spend money on the **front-end + LO cleanliness + IF ADC**, not on a GS/s vanity number at RF.
Open: do you need **full 28 GHz instantaneous capture**, or a **≤100–400 MHz channel at 28 GHz**? If it is the latter, say so — the IF / I/Q path is the practical answer and the jitter math stops being the blocker.
— rfforum 编辑部 / Editorial Team
1. **Why “just undersample 28 GHz” bites**
- Bandpass sampling needs the ADC/T/H **analog input bandwidth ≥ carrier**, not only fs > 2·B. A 5 GS/s converter with 1.5 GHz input BW does not see 28 GHz no matter which Nyquist zone you write on the whiteboard.
- Aperture jitter: SNR_jitter ≈ −20·log10(2π·f_in·t_j). At **f_in = 28 GHz**, even a loose **40 dB** SNR budget wants t_j on the order of **~18 fs RMS** (RSS of clock + ADC aperture). That is research-grade clocking + T/H, not an eval-board balun and a “low-jitter” CMOS PLL.
- So the wall is often **jitter × input BW**, not the sticker GS/s. A 60 GS/s part with mediocre aperture jitter still folds 28 GHz into mush.
2. **Practical prototype routes (what we actually bring up)**
1) **mmWave I/Q or single-mixer → IF, then RF-sampling / HS ADC** — still the default. Buy or module a 26–30 GHz downconverter (or beamformer IC with IF out), put anti-alias where it is cheap, sample at GS/s class. You own image / LO leakage / I/Q balance, which is easier than 20 fs at 28 GHz.
2) **Integrated mmWave RFSoC / FEMs** — when the SKU exists for your band: treat the on-chip mixer+ADC as the sampler; do not recreate it with a discrete 60 GS/s.
3) **True RF sampling at 28 GHz with external T/H** — reserved for demos where the T/H aperture and clock are the programme. Budget the jitter stack on paper before you PO the ADC; if you cannot name t_j and the clock tree, you are buying a very expensive IF aliaser.
3. **When sub-sampling *does* earn its keep**
- Carriers where commercial ADCs already have the **input BW** (roughly sub-6 to low-teens GHz today, part-dependent) and you can hold **≤50–100 fs** class jitter for your SNR target.
- Narrow instantaneous BW with heavy averaging / processing gain — still does not relax the *jitter* SNR floor on a CW tone; it only helps after the sampler is already clean enough.
- For a **28 GHz SDR prototype** whose goal is waveforms / beam / protocol, spend money on the **front-end + LO cleanliness + IF ADC**, not on a GS/s vanity number at RF.
Open: do you need **full 28 GHz instantaneous capture**, or a **≤100–400 MHz channel at 28 GHz**? If it is the latter, say so — the IF / I/Q path is the practical answer and the jitter math stops being the blocker.
— rfforum 编辑部 / Editorial Team
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