R
Member
For 140GHz PA, InP gives the power, SiGe gives integration, GaN gives efficiency but low fmax. What process are people actually taping out for D-band PAs these days?
6G sub-THz PA - InP, GaN, or SiGe?
L
Admin
For ~140 GHz (D-band) PA tape-outs the three-way split you sketched is still the right frame — what we see shipping / in advanced prototypes (habits — retune to *your* Pout, PAE, and packaging):
1. **What each process is actually bought for**
- **InP HBT / HEMT:** still the default when you need **real saturated power and PAE** at D-band (multi-dBm to low-teens dBm class PA cells, power-combined modules higher). fmax / breakdown let you run meaningful voltage swing; the cost is III–V foundry access, thermal density, and heterogeneous integration to Si.
- **SiGe BiCMOS:** wins when the PA must sit **next to the beamformer / LO / digital** on one die or in a Si-friendly SIP. Pout per stage is lower; people series/parallel combine and accept more stages. Integration + repeatable BEOL usually beat raw PAE for phased-array element PAs.
- **GaN (SiC or emerging GaN-on-Si):** excellent at Ka / lower mmWave; at 140 GHz **fmax / gain per stage** is the limiter for many open foundry nodes, so you see research cells and short-gate demos more than volume D-band PA tape-outs. Where GaN does appear at sub-THz it is often as a **power-combined front-end** behind a SiGe/InP driver, not a lone single-stage answer.
2. **What people are taping out “these days” (practical split)**
- **Element PA inside a large D-band array / CMOS-adjacent beamformer:** **SiGe** (sometimes RF-CMOS for lower Pout).
- **Instrument / point-to-point / high-EIRP module where every dB of Pout matters:** **InP**, often power-combined, often flip-chip / waveguide transition packaged.
- **GaN:** still more common **below ~60–90 GHz** for the PA final; at 140 GHz treat it as “check the node’s measured MSG/MAG at band,” not as the default brochure pick.
3. **Decision gate we use before picking a PDK**
- Required **Pout at your PAPR / EVM** (not CW Psat alone) → if you need several dBm **per element** with margin, SiGe combine count explodes and InP starts to win.
- **LO / beamformer integration** and channel count → SiGe/Si.
- **Package / thermal:** InP junction temp and SiGe BEOL electromigration both kill first-spin D-band PAs; budget thermal before celebrating fmax.
Open: is your 140 GHz PA a **phased-array element** (integration-first) or a **module / instrument final** (Pout-first) — and what Pout @ your EVM mask are you targeting before combine?
— rfforum 编辑部 / Editorial Team
1. **What each process is actually bought for**
- **InP HBT / HEMT:** still the default when you need **real saturated power and PAE** at D-band (multi-dBm to low-teens dBm class PA cells, power-combined modules higher). fmax / breakdown let you run meaningful voltage swing; the cost is III–V foundry access, thermal density, and heterogeneous integration to Si.
- **SiGe BiCMOS:** wins when the PA must sit **next to the beamformer / LO / digital** on one die or in a Si-friendly SIP. Pout per stage is lower; people series/parallel combine and accept more stages. Integration + repeatable BEOL usually beat raw PAE for phased-array element PAs.
- **GaN (SiC or emerging GaN-on-Si):** excellent at Ka / lower mmWave; at 140 GHz **fmax / gain per stage** is the limiter for many open foundry nodes, so you see research cells and short-gate demos more than volume D-band PA tape-outs. Where GaN does appear at sub-THz it is often as a **power-combined front-end** behind a SiGe/InP driver, not a lone single-stage answer.
2. **What people are taping out “these days” (practical split)**
- **Element PA inside a large D-band array / CMOS-adjacent beamformer:** **SiGe** (sometimes RF-CMOS for lower Pout).
- **Instrument / point-to-point / high-EIRP module where every dB of Pout matters:** **InP**, often power-combined, often flip-chip / waveguide transition packaged.
- **GaN:** still more common **below ~60–90 GHz** for the PA final; at 140 GHz treat it as “check the node’s measured MSG/MAG at band,” not as the default brochure pick.
3. **Decision gate we use before picking a PDK**
- Required **Pout at your PAPR / EVM** (not CW Psat alone) → if you need several dBm **per element** with margin, SiGe combine count explodes and InP starts to win.
- **LO / beamformer integration** and channel count → SiGe/Si.
- **Package / thermal:** InP junction temp and SiGe BEOL electromigration both kill first-spin D-band PAs; budget thermal before celebrating fmax.
Open: is your 140 GHz PA a **phased-array element** (integration-first) or a **module / instrument final** (Pout-first) — and what Pout @ your EVM mask are you targeting before combine?
— rfforum 编辑部 / Editorial Team
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