L
Admin
CW ACLR habits break the moment the DUT is TDD, pulsed radar, or a bursty Wi-Fi / cellular frame. A spectrum analyser in free-run peak-hold will happily average on and off slots into a number that neither matches the standard nor the PA’s real stress. Gating fixes that — if the gate is honest.
**1. What you are trying to capture**
- **On-slot** ACLR / SEM / occupied BW: only while the PA is transmitting at the power you care about.
- **Off-slot** leakage / residual: a different measurement; do not mix it into the on-slot trace.
- Habit: write on the plot **gate source, gate delay, gate length, and whether video/RF gate** — a screenshot without those is not reproducible.
**2. Trigger and gate alignment**
- Prefer a **frame / TX-enable / marker** trigger from the DUT or baseband, not “I guessed the period from the envelope.”
- Set gate delay/length from a zero-span or demod view of the same trigger so the gate sits inside the settled portion of the burst — not the ramp, not the symbol tail the standard excludes.
- If the analyser only offers periodic gate, measure the frame period carefully; a 1% period error walks the gate across the slot edge over a long sweep.
**3. RBW / detector traps that invent ACLR**
- Too-narrow RBW + short gate → not enough samples inside the gate → noisy or biased ACLR.
- Too-wide RBW → adjacent-channel energy from the main lobe skirts looks like ACLR fail.
- Peak detector + free-run on a pulsed signal → worst-case spikes from ramp / ALC / transient; RMS / average under a correct gate is usually what the radio standard wants — check the method, do not assume.
- Habit: after gating looks good, **disable the gate once** and confirm the trace changes the way you expect (on-slot rises, off-slot floor appears). If nothing changes, you were never gated.
**4. Level and front-end**
- Burst peaks still hit the mixer. Set attenuator / preamp for the **on-slot** crest, not the time-averaged power. Mixer-level lies from continuous-wave habits (see the SA mixer-level threads) get worse with pulsed DUT crest factor.
- External trigger cable delay is part of the measurement — leave it connected when you save the setup.
**5. A short gate sanity checklist**
1. Zero-span: gate box visibly inside the flat-top of the burst.
2. ACLR/SEM with gate on vs a known CW proxy at same Pout (if available) — order of magnitude should agree.
3. Shift gate ±10% of slot width: result should not jump more than your uncertainty unless you were sitting on the edge.
4. Save trigger source + gate params with the trace.
**Discussion**
On your last TDD or pulsed ACLR bring-up, what failed first — gate sitting on the ramp, wrong detector/RBW for the standard, or mixer overload on the burst peak — and do you trigger from a hardware TX-enable or from the RF envelope?
— rfforum 编辑部 / Editorial Team
**1. What you are trying to capture**
- **On-slot** ACLR / SEM / occupied BW: only while the PA is transmitting at the power you care about.
- **Off-slot** leakage / residual: a different measurement; do not mix it into the on-slot trace.
- Habit: write on the plot **gate source, gate delay, gate length, and whether video/RF gate** — a screenshot without those is not reproducible.
**2. Trigger and gate alignment**
- Prefer a **frame / TX-enable / marker** trigger from the DUT or baseband, not “I guessed the period from the envelope.”
- Set gate delay/length from a zero-span or demod view of the same trigger so the gate sits inside the settled portion of the burst — not the ramp, not the symbol tail the standard excludes.
- If the analyser only offers periodic gate, measure the frame period carefully; a 1% period error walks the gate across the slot edge over a long sweep.
**3. RBW / detector traps that invent ACLR**
- Too-narrow RBW + short gate → not enough samples inside the gate → noisy or biased ACLR.
- Too-wide RBW → adjacent-channel energy from the main lobe skirts looks like ACLR fail.
- Peak detector + free-run on a pulsed signal → worst-case spikes from ramp / ALC / transient; RMS / average under a correct gate is usually what the radio standard wants — check the method, do not assume.
- Habit: after gating looks good, **disable the gate once** and confirm the trace changes the way you expect (on-slot rises, off-slot floor appears). If nothing changes, you were never gated.
**4. Level and front-end**
- Burst peaks still hit the mixer. Set attenuator / preamp for the **on-slot** crest, not the time-averaged power. Mixer-level lies from continuous-wave habits (see the SA mixer-level threads) get worse with pulsed DUT crest factor.
- External trigger cable delay is part of the measurement — leave it connected when you save the setup.
**5. A short gate sanity checklist**
1. Zero-span: gate box visibly inside the flat-top of the burst.
2. ACLR/SEM with gate on vs a known CW proxy at same Pout (if available) — order of magnitude should agree.
3. Shift gate ±10% of slot width: result should not jump more than your uncertainty unless you were sitting on the edge.
4. Save trigger source + gate params with the trace.
**Discussion**
On your last TDD or pulsed ACLR bring-up, what failed first — gate sitting on the ramp, wrong detector/RBW for the standard, or mixer overload on the burst peak — and do you trigger from a hardware TX-enable or from the RF envelope?
— rfforum 编辑部 / Editorial Team
