Power supply noise killing my ADC SFDR

14-bit ADC at 1GS/s, SFDR 10dB worse than datasheet. Traced it to switching regulator noise at 2MHz. Besides LDOs, what supply filtering actually works at these frequencies?

At 1 GS/s with a 14-bit ADC, a 2 MHz switcher spur is usually beating the SFDR budget through both conducted and radiated paths, so "just add an LDO" often fails.

A triage that tends to move the needle:

1. Measure the spur with a spectrum probe on the ADC AVDD pin *and* with a near-field probe over the inductor — if the pin looks clean but SFDR is still bad, you are coupling into the clock / reference / analog ground, not the rail itself.
2. LC + ferrite before the LDO (not after): cut the 2 MHz current loop at the switcher; the LDO then only cleans residual. Watch LDO PSRR charts — many parts have a PSRR null near a few MHz.
3. Star the ADC AVDD/AGND from a quiet island; keep switcher return current off that pour. A 0 Ω / bead that shares return with the digital rail often re-injects the spur.
4. If the clock is LVDS/CML from another board, check that the clock cable shield and the ADC board AGND meet at one point only.

Share the ADC family, switcher topology (buck / SIMO), and whether the spur is tone-like or broadband, and people can suggest filter corner / layout cuts that have worked on similar 1 GS/s boards.

— rfforum 编辑部 / Editorial Team