L
Admin
[Technical article, rfforum Editorial Team]
Teams often freeze a conjugate match from a small-signal S22 or a single load-pull point, then discover that efficiency, ruggedness, or ACLR fall apart across the band or under VSWR. Contours exist for a reason.
1. What a single match point hides
- Optimum γ_L for Pout, PAE, and linearity are rarely the same point; a "max PAE" match can be the wrong place for your ACLR or video-bandwidth gate
- Contours move with drain voltage, temperature, and drive — a cold CW contour is not a hot modulated contour
- Source match / stability circles still matter on GaN; a load-only story that ignores Γ_S is incomplete bring-up
2. Freeze list for a first GaN MMIC / discrete line
- Which contour you optimise (Pout vs PAE vs a linearity proxy) and at which Vds / Pin / bandwidth
- VSWR ruggedness requirement: mismatch pull and shutdown behaviour belong in the same traveler as the "pretty" match
- Thermal boundary: case / flange temperature during contour collection — derate before you argue about 2% PAE
- Bias sequencing and gate clamp (/t/319 style) before any power sweep
3. Habit
Archive contour plots (or at least the chosen γ_L + the neighbouring contour that fails your gate) with the matching network BOM. Changing only the output network later without a bridge study invents phantom "device variance" between builds.
Discussion: on your last GaN bring-up, which gate failed first after freezing a single match — band-edge PAE, ACLR under modulation, or a VSWR event — and do you require a contour archive or only a final schematic?
— rfforum 编辑部 / Editorial Team
Teams often freeze a conjugate match from a small-signal S22 or a single load-pull point, then discover that efficiency, ruggedness, or ACLR fall apart across the band or under VSWR. Contours exist for a reason.
1. What a single match point hides
- Optimum γ_L for Pout, PAE, and linearity are rarely the same point; a "max PAE" match can be the wrong place for your ACLR or video-bandwidth gate
- Contours move with drain voltage, temperature, and drive — a cold CW contour is not a hot modulated contour
- Source match / stability circles still matter on GaN; a load-only story that ignores Γ_S is incomplete bring-up
2. Freeze list for a first GaN MMIC / discrete line
- Which contour you optimise (Pout vs PAE vs a linearity proxy) and at which Vds / Pin / bandwidth
- VSWR ruggedness requirement: mismatch pull and shutdown behaviour belong in the same traveler as the "pretty" match
- Thermal boundary: case / flange temperature during contour collection — derate before you argue about 2% PAE
- Bias sequencing and gate clamp (/t/319 style) before any power sweep
3. Habit
Archive contour plots (or at least the chosen γ_L + the neighbouring contour that fails your gate) with the matching network BOM. Changing only the output network later without a bridge study invents phantom "device variance" between builds.
Discussion: on your last GaN bring-up, which gate failed first after freezing a single match — band-edge PAE, ACLR under modulation, or a VSWR event — and do you require a contour archive or only a final schematic?
— rfforum 编辑部 / Editorial Team
