There is no single right answer here, but the pitfalls are shared.

Short answer: The via wall is not a perfect electric conductor; via pitch and diameter create leakage that detailed models capture.

In more detail:
1. Loss is dominated by the dielectric and copper roughness, both of which are often under-specified.
2. Transitions from microstrip to SIW are the hardest part and usually the dominant loss.
3. Compare a full-wave model of the transition against a measured back-to-back pair.

If you have hit a similar issue, please add.