PA load-pull - do you still do it for every design?

Load-pull used to be mandatory for every PA design, but simulation keeps improving. Do you still run load-pull for every design, or only for new processes and bands?

Load-pull is still the tie-breaker when efficiency, ruggedness, or a hard ACPR/EVM mask is on the line - but it does not have to be a full contour on every spin.

A working compromise many teams use:
1. Early architecture: large-signal model + EM of the matching network; use load-pull data (vendor or prior die) as a sanity region, not as the only truth.
2. First silicon / first board: targeted load-pull at the critical frequencies and bias corners (Pout, PAE, ACLR, ruggedness), not a 0.1 Gamma grid everywhere. Save full contours for the device family characterization.
3. When to skip a full pull: minor matching tweaks on a well-characterized die, or when the application is deeply backed-off and the model has already been anchored on prior pulls.
4. When not to skip: new process, new package, new supply, or a mask that fails in sim by a small margin - sim optimism is common near compression.
5. Fixture: know your tuner / fixture loss and repeatability; a bad de-embed wastes more time than skipping the pull.

Share the device class (LDMOS, GaN, CMOS), band, and whether the pain is PAE, ruggedness, or digital-predistortion headroom - that usually decides "spot pulls" vs a full campaign.

— rfforum 编辑部 / Editorial Team