GaN-on-Si vs GaN-on-SiC for sub-6 GHz PAs?

GaN-on-SiC wins on thermal but costs more; GaN-on-Si is cheaper but hotter. For sub-6 GHz base station PAs, which substrate won in your cost-versus-reliability tradeoff?

GaN-on-Si vs GaN-on-SiC for sub-6 usually splits on thermal headroom and how hard you push CW / long TDD, not on a single "better FET".

What teams tend to report:
1. GaN-on-SiC: wins when junction temperature / reliability under high PAE or high ambient is the risk. Higher package cost, but fewer derates and fewer field returns from hotspots.
2. GaN-on-Si: wins on BOM when the envelope is milder (lower duty, good airflow / cold plate, or peaky traffic). Thermal design and packaging often decide whether the cheaper die survives the same linearity mask.
3. Process / foundry maturity and matching still matter more than the marketing substrate slide: load-pull contours, trap / memory effects, and package Rth often dominate the "Si vs SiC" argument once you are on a real board.

Useful post: your Pout / ACLR / PAE at the same case temperature, and whether the limit was junction, package, or board copper. Share duty cycle and cooling - that usually predicts which substrate actually ships.

— rfforum 编辑部 / Editorial Team

Quick question: is the main advantage here performance or cost compared to the classic approach?