R
Member
On-wafer VNA work keeps teaching me the same lesson: the calibration kit matters more than the analyzer. A few notes from recent bench work.
First, SOLT is convenient but its accuracy is bounded by the standards themselves. The short and open on a typical ISS are not ideal at mmWave — the open radiates, the short has inductance — and those errors fold straight into your DUT data. Below 20 GHz this rarely bites; above 40 GHz it starts to show up as ripple you cannot explain away.
Second, TRL earns its keep when the reference plane matters. TRL puts the reference plane at the probe tips using a thru and a line, so the probe and pad parasitics drop out of the result. The cost is time: you need a line standard whose electrical length sits between 20 and 160 degrees at every frequency you care about, which usually means two or three lines for a wide sweep.
Third, the line standard is where people get sloppy. A line with the wrong impedance, or a line measured with a bad probe contact, corrupts the whole calibration — and the VNA will happily report a "successful" calibration. I always check the calibrated thru measurement after TRL: if the thru does not read back near 0 dB insertion loss and 0 degrees, something is wrong with the standards, not the DUT.
Fourth, hybrid approaches are legitimate. Use SOLT for a fast sanity check, then switch to TRL for the data you will actually publish or ship. And re-verify with a check standard — a known attenuator or a verification line — at the end of the session, not just at the start.
What is your default on-wafer calibration flow, and at what frequency do you stop trusting SOLT?
First, SOLT is convenient but its accuracy is bounded by the standards themselves. The short and open on a typical ISS are not ideal at mmWave — the open radiates, the short has inductance — and those errors fold straight into your DUT data. Below 20 GHz this rarely bites; above 40 GHz it starts to show up as ripple you cannot explain away.
Second, TRL earns its keep when the reference plane matters. TRL puts the reference plane at the probe tips using a thru and a line, so the probe and pad parasitics drop out of the result. The cost is time: you need a line standard whose electrical length sits between 20 and 160 degrees at every frequency you care about, which usually means two or three lines for a wide sweep.
Third, the line standard is where people get sloppy. A line with the wrong impedance, or a line measured with a bad probe contact, corrupts the whole calibration — and the VNA will happily report a "successful" calibration. I always check the calibrated thru measurement after TRL: if the thru does not read back near 0 dB insertion loss and 0 degrees, something is wrong with the standards, not the DUT.
Fourth, hybrid approaches are legitimate. Use SOLT for a fast sanity check, then switch to TRL for the data you will actually publish or ship. And re-verify with a check standard — a known attenuator or a verification line — at the end of the session, not just at the start.
What is your default on-wafer calibration flow, and at what frequency do you stop trusting SOLT?
