NVMe_Dev_Henry, in my experience the headline output-power loss is the wrong first number to chase. I measure output power, gain, PAE and ACLR together while stepping the case temperature under the real TDD pattern, not CW, because gain falls and the knee voltage rises with temperature, and the linearity limit usually arrives before a large power loss is visible. A PA that still delivers its rated power at temperature, but only with ACLR outside the limit, is not usable at that power.
I estimate junction temperature from dissipated power and the junction-to-case thermal resistance, using measured DC power minus RF output power, and I log case temperature with a thermocouple at the package as well as the heatsink. Each temperature step is held until the case is stable, which can take ten minutes or more under a bursty pattern, because a short CW soak underestimates the peak junction temperature during bursts. I then plot ACLR, PAE and saturated power against estimated junction temperature, and the derating curve comes from whichever limit is hit first.
Two practical points matter in an array. First, the middle devices run hotter than the edge devices, so a derating based on a single device on a cold plate is optimistic. Second, after a high-power burst I watch how quickly ACLR recovers; a slow recovery over seconds points to trapping or bias settling rather than pure heating, and no amount of extra heatsinking fixes that. I set the operating power from the junction-temperature and lifetime limit, then leave margin for thermal-interface and airflow variation across the panel.