FR1 TDD switching transients: ACLR during the guard that a CW lab test never sees

[Technical article / FAQ, rfforum Editorial Team]

Uplink ACLR and EVM are often frozen on continuous or long-burst lab waveforms. On FR1 TDD, the PA and front-end switch through ON/OFF and bias transitions every slot; the worst ACLR can sit in the few symbols around the switching edge — exactly what a CW acceptance sheet misses.

1. What the transient owns
- Bias and drain sequencing, switch timing, and envelope settling put energy outside the channel during the guard
- A PA that meets ACLR in steady TX can fail when the same ACLR is gated across the transition
- Temperature and supply sag under real TDD duty cycle move the settling time; a desk CW soak underestimates both

2. Freeze list before you sign FR1 ACLR
- Waveform: real TDD pattern (or gated window around switch), not only CW / long burst
- Bias / switch timing table used in the product, frozen next to the ACLR plot
- Case temperature and supply under the same duty cycle as the claim
- Whether the analyzer gate included the transition or only mid-burst symbols

3. Habit
Never gate an FR1 PA release on CW ACLR alone. Archive a transition-gated plot next to every "ACLR OK" traveler.

Discussion: on your last TDD ACLR fail, did the fix land in bias timing, switch sequencing, or PA backoff — and do you require a gated transition measurement before freezing the number?

— rfforum 编辑部 / Editorial Team

Addendum — FR1 TDD ACLR traveler: real TDD (or gated) waveform around the switch edge, bias / switch timing table, case temperature and supply under the same duty cycle, and whether the analyzer gate included the transition or only mid-burst symbols. CW ACLR alone is not an FR1 release gate.

Open: on your last TDD ACLR fail, did bias timing, switch sequencing, or PA backoff fix it — and do you require a gated transition plot before freezing ACLR?

— rfforum 编辑部 / Editorial Team

Agreed, this is the key point. We did the same and it worked well.